Company
Arm is a UK-based chip designer whose energy-efficient architecture is licensed to most mobile and embedded processor makers worldwide.
AMD rose 32% and Intel 21% in a month as Meta's Muse and OpenAI's Dots ran long-running AI agents on CPUs. The cash behind the move depends on how many agent sessions run and whose processors they run on.
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OpenAI runs its Jalapeño ASIC on AMD EPYC Turin hosts with 1.5TB of memory each, chosen over Nvidia's Vera because Vera is less mature. Richard Ho tied the call to one program's schedule and a first-generation chip, so it says little about x86 against Arm.
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Domenec Forte of the University of Florida says AI chip-design agents can spread an infringed patent across thousands of chips before anyone notices. Teams piloting these tools take on that risk at production volume, while the law on who answers for an agent's accidental copy is unsettled.
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VUSec disclosed Branch Target Reuse, a Spectre-v2 attack on JIT engines whose Linux exploit leaks memory at 8 bytes a second. It bypassed every enabled mitigation, and the kernel's fix had already shipped in July.
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Intel, AMD and Arm say their IBPB barrier can block Branch Target Reuse, a Spectre v2 variant hitting all three, if JIT software calls it. Each kernel, browser and runtime that rewrites JIT code now has to add that call itself.
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Nuvacore is designing a significant part of its WarpCore data-center CPU before choosing between Arm, RISC-V and x86. The startup gets to make the instruction-set decision later, though whichever one it picks still has to shape the front end and parts of the rest of the core.
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Nvidia announced its Open Agent Safety Platform with more than 100 companies behind it, none of them OpenAI, Amazon, Google or Apple. For teams running agents, it is a widely backed Nvidia stack that still falls short of an industry standard.
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A Bitcoin-mining chip designer has rebranded as an AI silicon IP vendor, and the pitch it raised on is power per matrix multiply rather than peak performance.
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The Mali G2-Ultra NX is on sale in mainland China now, but Arm says super sampling comes first, frame generation in early 2027 and denoising after that, so Android teams get the render path well before the full payoff.
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Absmax INT8 takes one scale from the largest magnitude in a tensor, so a single outlier sets the step size for everything else. The LLM.int8() authors found those outliers sitting in about six feature dimensions.
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The $10bn SoftBank owes OpenAI on 1 October is the exact size of the dollar leg of the bond it prices on 24 September. Yields on its 2031 paper have moved from 6.7% in January to about 8.2% in September.
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Apple has not confirmed the plan and the M8 Ultra is years from release. Seven other companies have already licensed the same rack interconnect from Nvidia, and their dates are the ones a buyer can use.
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Reuters says Anthropic is discussing a listing that would raise up to $100 billion at about $2 trillion, roughly double May's private mark, with Nvidia weighing $10 billion of the book. The raise sells about 5 percent of the company.
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The Ensemble parts run Arm's Cortex-M55 cores and Ethos-U55 NPUs, so what Analog Devices is buying for up to $1.55B is the integration around them and a distribution channel Alif could not build alone.
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The uplift runs through the regular instruction pipeline, so adopting it costs a developer a compile step. That changes what an accelerator-specific inference path has to prove before a team keeps paying to maintain it.
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Nvidia's argument is that a slice of inference moves from the server farm to the desk. The case rests on one publisher's account of a Computex launch, and the memory spec that would settle it is not in there.
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Two 70-core N3P chiplets, 12 DDR5 channels and a 2 TB/s UCIe link give capacity planners something to price. The 844.8 GB/s peak assumes DDR5-8800 modules Tom's Hardware says have not reached market.
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The AGI CPU is a 136-core Neoverse part co-designed with Meta. Arm's pitch to custom-silicon customers used to be that it had nothing of its own to sell.
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One SKU, one compute die, 1.2 TB/s of LPDDR5X, and benchmark wins over a 96-core EPYC. The comparison with AMD's Venice is being set on Nvidia's terms rather than on core counts.
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The dual-ISA core runs AArch64 and z/Architecture on the same core with nanosecond switching. x86 is named in the pitch and absent from the silicon, and the uptime arithmetic does not close.
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