CXMT's two 50 per cent claims multiply to 2.25 times the bits per wafer

The two 50 per cent figures multiply. If the die-count gain and the capacity gain sit on one baseline and one wafer size, bits per wafer come out 2.25 times higher than the generation before ^[10].

Whether they sit on one baseline is the open question. CXMT gave the die-count gain against its previous technology platform, and the capacity gain against the previous generation of similar products ^[4][5]. The statement does not reconcile the two. The product figure is the firmer of them: a 24-gigabit die that is half again the capacity of its predecessor implies a 16-gigabit predecessor ^[7], 2 gigabytes going to 3 ^[8].

Dies per wafer is the input a memory maker controls most directly. Processing a wafer costs what it costs, so 50 per cent more dies on it takes wafer cost per die to two thirds of the old number, a cut of about 33 per cent ^[12]. That holds only if yield per die does not fall and the extra patterning does not make the wafer dearer to run, and CXMT credits the node to "quadruple exposure" ^[3].

On the labels, 11.95nm sits 1.95nm above the 10nm process that the South China Morning Post attributes to Samsung and SK Hynix, roughly 20 per cent coarser ^[11][9].

A cost floor under commodity and mobile DRAM needs shipped bits at a price. CXMT's statement does not include yields, wafer starts or prices ^[6]. In my view the 2.25 figure is the one to test, because LPDDR5X parts get bought and opened, and a die measurement settles the density question without the company's help. The counter-case is narrower and duller: mass production here covers two 24-gigabit mobile parts ^[5], the older platform can carry most of the output, and a true density claim then changes nobody's cost floor this year.

The thesis fails if a teardown puts the 24-gigabit part's bit density well short of 2.25 times the 16-gigabit one, or if the 50 per cent counts dies printed and not dies sold. CXMT called the density gain a "quantum leap" ^[4].